Can AMD's Cool'n'Quiet kill my CPU and PSU? - processors amd - order by pertinence

Penguin Computing Announces Availability of AMD Opteron™ 6200 and 4200 Series Processors and Large Scale Deployment

First Successful Interlagos Deployment in Operation at University of Delaware.

Press published on the November 14th, 2011 - 9:59 AM ET

Jon Peddie Research Reports Nvidia led Q3 With 20% Quarter-to-Quarter Growth—AMD and Intel Dropped

Holding steady: 34.3 Million discrete GPUs shipped, 4.5% over last quarter but declined 5.2% from last year. There was a 4.5% dip in overall graphics shipments in Q3 from last quarter..

Press published on the November 26th, 2012 - 11:12 AM ET

Nvidia Winner in Q1, AMD Flat, Intel Down says Jon Peddie Research

Quarter-to-quarter negative 2.9%—Desktop discrete sales up.

Press published on the May 17th, 2013 - 11:48 AM ET

Jon Peddie Research Reports AMD, Intel, and Nvidia All Down in Q4 with Negative 8% Overall Quarter-to-Quarter Decline

Holding steady: 28.8 Million discrete GPUs shipped, down almost 16% over last quarter and declined 9.7% from last year. There was an 8.2% dip in overall graphics shipments in Q4 from the third quarter..

Press published on the February 19th, 2013 - 6:00 AM ET

CyberLink Releases Product Updates – Optimized for AMD Fusion Family of APUs

Delivering an Enhanced and Accelerated Media Experience.

Press published on the February 17th, 2011 - 7:00 AM ET

ArcSoft Demonstrates Applications Optimized for GPU Compute and the AMD Fusion Family of APUs at CES 2011

Hardware accelerated video playback and faster file conversion on PCs.

Press published on the January 6th, 2011 - 8:00 AM ET

GLOBALFOUNDRIES and ARM Deliver Optimized SoC Solution Based on ARM Cortex-A Series Processors

Companies achieve milestones for SoC based on ARM Cortex-A9 processor: 28nm SoC operating at 2.5GHz and tape out of 20nm qualification vehicle.

Press published on the December 14th, 2011 - 4:00 PM ET

Can AMD's Cool'n'Quiet kill my CPU and PSU?

Hello. A few days ago, I came home to my already powered on old Linux/Debian computer desktop (leave it mostly 24/7). I woke it up to log in from its xmatrix screen saver and sleep. I ran a program (just upgraded VirtualBox and wanted to test it) ...

Message posted on the December 5th, 2009 - 5:35 PM ET

[PATCH RESEND 0/3] perf, amd: Support for Family 16h L2I Performance Counters

Upcoming AMD Family 16h Processors provide 4 new performance counters to count L2 related events. Similar to northbridge counters, these new counters are shared across multiple CPUs that share the same L2 cache. This patchset adds support for these ...

Message posted on the April 9th, 2013 - 11:30 AM ET

[PATCH 0/3] perf, amd: Support for Family 16h L2I Performance Counters

Upcoming AMD Family 16h Processors provide 4 new performance counters to count L2 related events. Similar to northbridge counters, these new counters are shared across multiple CPUs that share the same L2 cache. This patchset adds support for these ...

Message posted on the March 27th, 2013 - 6:10 PM ET

[PATCH 1/3] x86, AMD: Change Boris' email address

Move to private email and put in maintained status. Signed-off-by: Borislav Petkov <bp@alien8.de> arch/x86/kernel/cpu/mcheck/mce_amd.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/kernel/cpu/mcheck/mce_amd.c ...

Message posted on the October 29th, 2012 - 12:50 PM ET

[PATCH] x86/amd: Fix L1i and L2 cache sharing information for AMD family 15h processors

For L1 instruction cache and L2 cache the shared CPU information is wrong. On current AMD family 15h CPUs those caches are shared between both cores of a compute unit. This fixes https://bugzilla.kernel.org/show_bug.cgi?idB607 Signed-off-by: ...

Message posted on the February 8th, 2012 - 3:00 PM ET

[PATCH] x86, Remove AMD microcode warning

AMD processors will never support /dev/cpu/microcode updating so just silently fail instead of printing out a warning for every cpu. Signed-off-by: Prarit Bhargava <prarit@redhat.com> Cc: Borislav Petkov <borislav.petkov@amd.com> Cc: ...

Message posted on the February 6th, 2012 - 2:30 PM ET

[PATCH 0/4] x86, amd: family 0x15 L3 cache features

This patch set applies to tip/x86/amd-nb f658bcfb. It enables L3 cache index disable and adds support for L3 cache partitioning on family 0x15 CPUs. Andreas Herrmann (1): x86, amd: Normalize compute unit IDs on multi-node processors Hans Rosenfeld ...

Message posted on the December 20th, 2010 - 12:20 PM ET