[PATCH] perf, x86: Optimal way of reading LBR entries inside Intel PMU interrupt handler

perf, x86: Optimal way of reading LBR entries inside Intel PMU interrupt handler We read LBR entries even if no event has requested for it either explicitly through branch sampling or implicitly through precise IP. This patch would fix this ...

Message posted on the May 22nd, 2012 - 7:30 AM ET

Schooner Information Technology Announces Flash-Optimized MySQL with InnoDB on All Dell, HP and IBM x86 Servers

Schooner Broadens Its Solution to Meet Customer Preferences of Hardware and Flash Memory.

Press published on the February 1st, 2011 - 7:00 AM ET

Schooner Information Technology Announces Membrain: the Smart NoSQL Data Store, Based on Memcached

Schooner Software Brings High-Performance Flash-Optimized Cache and Data Store to Dell, HP and IBM x86 Servers.

Press published on the February 1st, 2011 - 7:00 AM ET

ScaleMP™ Provides Fujitsu with vSMP Foundation Hardware Certification

ScaleMP vSMP FoundationTM and PRIMERGY x86 Servers Combine to Create a Powerful SMP Solution for HPC Systems.

Press published on the September 15th, 2011 - 9:16 AM ET

Schooner Information Technology Releases Membrain™ 4.0

Superior Software Cache and Data Store Provides Massive Server Consolidation, Optimal Performance and Minimal Downtime in Datacenters.

Press published on the March 13th, 2012 - 6:00 AM ET

AIS Releases a Open Architecture Operator Interface Terminal for Industrial, Infrastructure and Facility Processes Applications

American Industrial Systems Inc. (AIS), is an ISO 9001:2008 certified supplier and manufacturer of a X86-based 15”operator interface terminals, fully equipped an industrial touch panel display, Intel 1.6GHz ...

Press published on the October 31st, 2011 - 11:15 AM ET

SGI Customers Accelerate Research Efforts With New AMD Opteron™ 6200 Series Processors

Industry-Leading x86 Cores per Socket Power Terrestrial to Cosmic Applications.

Press published on the November 14th, 2011 - 3:15 PM ET

Benefits of virtualization

In an environment that is increasingly competitive, as well encountering problems when trying to adapt to environmental constraints, companies require solutions that allow them to generate optimal performance/cost ratios. A typical example is the ...

Review published on the December 4th, 2009 - 1:40 AM ET

[RFC] x86: mtrr: Constrain WB MTRR to max phys mem prior to cleanup

If BIOS maps all or most of the phys address space as write-back, regardless of the amount of actual RAM, then mtrr_cleanup may create superfluous MTRR entries, or may be unable to create an optimal map (or may use all MTRRs attempting to do so, ...

Message posted on the September 7th, 2012 - 2:00 PM ET

mtrr_cleanup: can not find optimal value

Hi there, I'm suffering bad graphic performance on my notebook, and when sorting things out, I found the following in dmesg: mtrr_cleanup: can not find optimal value please specify mtrr_gran_size/mtrr_chunk_size and later: mtrr: type mismatch ...

Message posted on the June 3rd, 2011 - 1:20 AM ET

[PATCH 2/2]x86: spread tlb flush vector between nodes

Currently flush tlb vector allocation is based on below equation: sender = smp_processor_id() % 8 This isn't optimal, CPUs from different node can have the same vector, this causes a lot of lock contention. Instead, we can assign the same vectors to ...

Message posted on the October 19th, 2010 - 11:10 PM ET

[patch]x86: spread tlb flush vector between nodes

Currently flush tlb vector allocation is based on below equation: sender = smp_processor_id() % 8 This isn't optimal, CPUs from different node can have the same vector, this causes a lot of lock contention. Instead, we can assign the same vectors to ...

Message posted on the October 13th, 2010 - 3:50 AM ET

[PATCH] x86, hotplug: Fix powersavings with offlined cores on AMD

From: Borislav Petkov <borislav.petkov@amd.com> ea53069231f9317062910d6e772cca4ce93de8c8 made a CPU use monitor/mwait when offline. This is not the optimal choice for AMD wrt to powersavings and we'd prefer our cores to halt (i.e. enter C1) ...

Message posted on the January 20th, 2011 - 9:50 AM ET

Re: + x86-mm-handle-mm_fault_error-in-kernel-space.patch added to -mm tree

(add cc's) Subject: x86/mm: handle mm_fault_error() in kernel space From: Andrey Vagin <avagin@openvz.org> mm_fault_error() should not execute oom-killer, if page fault occurs in kernel space. E.g. in copy_from_user/copy_to_user. Why? ...

Message posted on the March 10th, 2011 - 9:40 AM ET

x86 optimal