x86, perf, pmu: make reserve_ds_buffers() allocate memory dynamically

Hi guys, Some kdump folks noticed that on large machines (say 80 cpu threads), the kernel reserved a good chunk of memory in the kdump kernel with the call to reserve_ds_buffers(). About 64k per cpu. Normally the kdump kernel boots with maxcpus=1 ...

Message posted on the June 24th, 2011 - 12:10 PM ET

[RFC] perf, x86: Segregate PMU workaraunds into x86_pmu_quirk_ops structure

Hi, I would appreciate comments/complains on the following patch. The idea is to implement PMU quirks with minimal impact. At the moment two quirks are addressed - PEBS disabling on Clovertown and P4 performance counter double write. PEBS disabling ...

Message posted on the May 29th, 2010 - 2:30 PM ET

[PATCH -tip] perf, x86: P4 PMU -- redesign cache events

From: Cyrill Gorcunov <gorcunov@openvz.org> Subject: [PATCH -tip] perf, x86: P4 PMU -- redesign cache events To support cache events we have reserved low 6 bits in hw_perf_event::config (which is a part of CCCR register configuration ...

Message posted on the July 4th, 2010 - 10:20 PM ET

perf PMU support for Haswell v7

[Updated version for the latest master tree and fixes. See end for details. All feedback addressed. Ready for merging.] This adds perf PMU support for the upcoming Haswell core. The patchkit is fairly large, mainly due to various enhancement for ...

Message posted on the January 17th, 2013 - 3:50 PM ET

perf PMU support for Haswell v8

This is a heavily updated version of the Haswell PMU TSX and other patchkit, on top of the separate "basic haswell" patchkit This adds perf PMU support for the upcoming Haswell core. The patchkit is fairly large, mainly due to various ...

Message posted on the April 20th, 2013 - 3:30 PM ET

perf PMU support for Haswell v6

[Updated version for the latest master tree and various fixes, addressing review feedback. See end for details. This should be ready for merging now, just waiting for Peter&Ingo.] This adds perf PMU support for the upcoming Haswell core. The ...

Message posted on the November 9th, 2012 - 8:40 PM ET

[rfc] x86,perf: P4 PMU -- use hash for p4_get_escr_idx

Hi Ming, could you give this patch a shot if possible? Compile tested only. I would appreciate review and complains as well :) I know you're busy with other perf task so there is no hurry. Just to share the patch as early as possible. Have CC'ed a ...

Message posted on the May 10th, 2010 - 11:30 AM ET

[RFC][PATCH 00/13] perf pmu interface changes -v3

The first 5 patches are fixes to the existing code and should probably end up in .35, Dave has his sparc64 fix already queued I think, Paulus could you take the FSL fixes? The rest of these patches prepare the perf code for multiple pmus (no user ...

Message posted on the July 9th, 2010 - 4:50 AM ET

perf PMU support for Haswell v5

[Updated version for the latest master tree and various fixes, addressing review feedback. See end for details. This should be ready for merging now. Arnaldo, especially needs attention from you for the user space part.] This adds perf PMU ...

Message posted on the October 30th, 2012 - 7:40 PM ET

perf PMU support for Haswell v3

[Updated version for the latest master tree and various fixes. See end for details. This should be ready for merging now I hope.] This adds perf PMU support for the upcoming Haswell core. The patchkit is fairly large, mainly due to various ...

Message posted on the October 18th, 2012 - 7:30 PM ET

perf PMU support for Haswell

This adds perf PMU support for the upcoming Haswell core. The patchkit is fairly large, mainly due to various enhancement for TSX. TSX tuning relies heavily on the PMU, so I tried hard to make all facilities easily available. In addition it also has ...

Message posted on the September 28th, 2012 - 12:40 AM ET

[PATCH] x86,perf: P4 PMU -- fix misprint in unflagged nmi handling

From: Cyrill Gorcunov <gorcunov@openvz.org> Subject: [PATCH] x86,perf: P4 PMU -- fix misprint in unflagged nmi handling Tested-by: Lin Ming <ming.m.lin@intel.com> Signed-off-by: Cyrill Gorcunov <gorcunov@openvz.org> ...

Message posted on the May 18th, 2010 - 5:40 AM ET

[PATCH] x86,perf: P4 PMU -- handle unflagged events

From: Cyrill Gorcunov <gorcunov@openvz.org> Subject: [PATCH] x86,perf: P4 PMU -- handle unflagged events It might happen that event if being overflowed without proper bit set. Check the sign bit in counter. Tested-by: Lin Ming ...

Message posted on the May 17th, 2010 - 4:20 AM ET

perf PMU support for Haswell v4

[Updated version for the latest master tree and various fixes. See end for details. This should be ready for merging now I hope. Arnaldo, especially needs attention from you for the user space part.] This adds perf PMU support for the upcoming ...

Message posted on the October 26th, 2012 - 4:40 PM ET

x86 perf pmu